The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure containing a vertical transistor having air gap spacers located above and below each functional gate structure, and a method of forming the same.
Conventional vertical transistors are devices where the source-drain current flows in a direction normal to the substrate surface. In such devices, a vertical semiconductor pillar defines the channel with the source and drain located at opposing ends of the semiconductor pillar. One advantage of a vertical transistor is that the channel length is not defined by lithography, but by methods such as epitaxy or layer deposition, which enable precise dimensional control.
As such, vertical transistors are an attractive option for technology scaling for 5 nm and beyond. The increasing density in those technology nodes has the effect of increasing the parasitic capacitance between the gate and the source/drain epitaxy. There is thus a need for providing vertical transistors for use in future technology nodes in which the parasitic capacitance has been reduced.